Physical Design Interview Questions

1 What is LEF

2 What isDEF

3 Types of timing paths:

Multicycle paths:

Both Tran and timing optimizations are done on these paths

False paths:

Only transition optimizations are done.

Disable timing arc:

No optimization for transition and Timing are done.

4 Have you done power planning?

A) If so draw the structure.

B) What are the metal layers used?

5 When you import design what are all the things you need to check?

LEF, SDC, NETLIST, Cell & Macro libraries, Floorplan.

6 What are the checks you perform after Floorplan?

Tap cells, Decaps, End caps, Macros placement, Soft blockage between Macros.

7 How do you reduce Dynamic power leakage?

Clock gating, Power gating [Temporary switching off of the module done by using Cadence [CPF]/UPF[Synopsys] flow] and Dynamic Voltage Frequency Scaling [DVFS]

8 How do you reduce Static Power Leakage?

Multi VT cells [HVT, RVT, LVT]

HVT – has Higher threshold Voltage [large delay, less leakage]

RVT – has moderate threshold voltage [Normal delay, normal leakage]

LVT – has Low threshold voltage [ Small delay, High leakage]

9 How do you address Congestion?

Types of congestion are: Routing and Placement

By using place guides, density screens and cell padding.

10 What is the use of Decaps?

To support the power hungry modules in the design we use decaps.

They are leaky.

11 Why do we have Tap cells?

To avoid latch up.

Tap cells internal structure:

Nwell is connected to VDD and Substrate to Ground.

12 What is latch up?

Formation of thyristor.

13 What is the content of the CTS Spec file:

Type of Buffers/Inverters.

NDR Rules.

Metals to be used.

Skew specifications.

Clock groups declaration.

14 What is the main aim of CTS?

Latency,Skew and power.

15 Why do we check Hold after CTS?

Actual skew is seen after CTS.

16 How much is hold uncertainity in the design or what are the components of hold uncertainity.

We only have margin for Hold uncertainity no Jitter component will be there.

17 Will there be difference between Uncertainty PRECTS & POSTCTS SDC?

Yes. Skew will be different.

18 What is OCV?

To accommodate On Chip Variation effectds we use derates.

19 How are derates applied for Setup & Hold:

Setup:

Data path will be slow clock path will be fast.

Hold:

Data path will be fast clock path will be slow.

20 What are electrical DRCs?

Tran & Cap [Slew].

21 What is AOCV?

Advanced OCV is categorized into two sections:

Depth and Distance based.

As Depth increases derates decreases.

As Distance increases derates increases.

22 What is CPPR?

Delta difference between the derates applied on the Common path of the clock.

23 How will be CPPR for Half cycle path?

24 What is Clock reconvergence?

When you have two Clocks asynchronous A & B. And if there are paths from A and B to clock domain C.

In that case you need to build the clock for those points separately.

25 Can a Flop to Flop path have both Setup & Hold violations?

Yes. It can have.

How do you approach then?

The path traced for setup and hold will be different if there is a huge combo logic between those two flops.

26 Draw the structure of Clock Gating cell.

27 What happens if there is Clock Gating Check?

There will be a Glitched Clock waveform.

28 Why do we latch why cant we use directly AND gate or FLOP for clock gating?

If we use and we get clipped waveform

You can’t use flop as it is edge sensitive.

Latch is level based and it is open once there is a change in level. So when ever the signal comes you can acknowledge it.

29 Which are good for CTS, Inverters & Buffers?

We can use both. We can even use a mix of both Buffer and Inverter.

30 What is LVS, What are the inputs, What are the issues?

Layout Vs Schematic.

Netlist, GDS, Rule deck and text file for pin location co-ordinates.

Opens and Shorts, Device Mismatches.

31 What is LEC?

Logical Equivalance check. Mention any issues if you have faced.

32 Inputs for IR Analysis?

Libraries, Netlist Spef,

33 Inputs for Calibre?

GDS, Ruledeck

34 Can we do close DRC using PnR and without using Calibre?\

Yes we can but to check DRCs in PnR we don’t have base layer information.

Even if you provide it will take long run times to fix it.

35 Why do we use Primetime for STA Signoff?

We use because the results of PT match with SPICE simulations.

36 Why do we use multi cut via?

For yield.

37 What are half nodes?

40nm 28nm.

38 How to estimate the gap between the macros?

Pin count and the metal resources availability.

39 Why do we do metal fill?

To address Chemical Mechanical Processing stress.

It will affect timing.

40 What is crosstalk and How does it affect?

Because of coupling capacitance we see a faster or slower delay in the design.

Glitch causes logical failure.

We don’t have to fix crosstalk completely in the design.

41 What are the components of Leakage?

Dynamic = CV^2f

Static= Based on V threshold.

Shortcircuit.

41 How do you optimize power?

By swapping the cells in the paths which has sufficient slack

42 How do you fix setup & Hold?

Skew,

Tran fix,

Cap fix,

VT Swap,

43 What is useful skew?

http://vlsi-soc.blogspot.in/2013/03/clock-skew-implication-on-timing.html

44 What is temperature inversion?

At lower nodes as the temperature increases the Threshold voltage decreases.

Because of which at lower nodes the slow corner is not high temperature one. It is with low temperature one.

Examples:

Slow corner:

0.945V_0.945v_ss_cw_-30C

Fast Corner:

1.26v_1.26V_ff_cb_125C

45 What is CW, CB, RCW & RCB?

Cworst: Metal size will be more increasing the Coupling cap.

Cbest: Metal size will be less decreasing the Coupling cap.

Product of RC will be Worst: R will be dominant here. So. Long nets will get affected.

Product of RC will be Best: R will be less here. So, Cell delays are dominant here.

46 IR Fixes?

47 If you have to tweak skew what will you look for to fix the path?

You will check whether sufficient skew is available for next path or not

48 Huge tran violation will cause:

Short circuit leakage and vulnerable to crosstalk effects.

49 Tran violation is seen on Input pins; Cap violations on Output pins.

50 Instead of NLDM models now a days they are using TLU Plus files for timing at placement.

This is because if you are using Physical synthesis [using DC Topography from synopsys].

Here Synthesis is done based on the Floorplan DEF provided by PD engineer to synthesis person. Where timing and Electrical DRC/DRV optimization is done.

51 CCS timing models are nothing but,

Timing information based on Different Capacitance loads.

They even accommodate Miller effect

52 How do you place macros if no flow diagram is provided?

By opening netlist and identifyin by the name.

53 If the whole path is optimized for Hold and setup and if there is still violation how do you fix them?

For Setup : Swap the Endpoint Flop to LVT to fix.

For Hold: Swap the Endpoint Flop to HVT to fix.

54 What is setup & Hold?

55 CTS can be done in multi mode or Single mode.

Single mode is preferred as run times are small and Delta difference in skew will almost same across modes.

56 What is GBA and PBA.

Graph Based Analysis Where worst delay is taken through a cell while delay calculation.

Path Based Analysis Where exact pin delay is taken through a cell while delay calculation.

57 Inputs for STA:

DEF, NXTGRD & Netlist for detailed extraction of SPEF

Then the above SPEF and NETLIST and Libraries.

For a quick STA run SPEF Libraries and Netlist using all the sub chips spef and netlist. Some time even DBs.